In fabrication of silicon semiconductor based high speed integrated circuits, the integration of both CMOS (complementary metal oxide semiconductor transistors) and bipolar transistors to provide Bipolar-CMOS (BiCMOS) VLSI integrated circuits is now well established for telecommunications applications requiring high speed, high drive, mixed voltage and analog-digital performance. However, there is considerable challenge in optimizing the performance of both CMOS and bipolar devices fabricated with progressively reduced dimensions. A manufacturable fabrication process for minimum geometry integrated circuits must be provided without inordinately increasing the process complexity, i.e. the number of mask levels and process steps.
Bipolar transistors having an emitter-base-collector structure in either a vertical or a lateral configuration are known. Key parameters that must be reduced to increase switching speed are base width, base transport time, base resistance and base-collector capacitance.
In combining shallow junction CMOS transistors with bipolar transistors for a sub-micron BiCMOS VLSI integrated circuit, a vertical bipolar transistor is commonly used. For example, a vertical PNP bipolar transistor comprises a buried collector formed in a P type region of the substrate, a heavily N doped base region is provided in the substrate surface and an heavily P doped emitter region overlies an active base region, forming an emitter-base junction. Base contacts are provided to the base region of the substrate surface adjacent the active base region. Contact to the buried collector is made through a heavily P doped region (i.e. a sinker) extending to the substrate surface. A vertical bipolar transistor with a shallow base width may be obtained in a process compatible with forming shallow junctions for CMOS transistors. For example, a bipolar transistor with a base width of -0.2 .mu.m may be achieved by low energy ion implantation, or by diffusion of impurities from an overlying heavily doped layer.
On the other hand, a conventional lateral bipolar transistor differs in structure considerably from a vertical bipolar transistor. A typical PNP lateral bipolar transistor comprises a substrate on which is formed a P doped epitaxial layer. Heavily P doped regions are defined in the epitaxial layer to form an emitter and a collector. The latter are defined by ion implantation of surface regions. The active base region is provided by the N doped layer disposed between the emitter and the collector, the base width being defined by the lateral spacing of the emitter and the collector. A buried base contact is provided by an underlying heavily N doped base electrode region. Thus, in a lateral bipolar transistor of this structure, the base width is constrained to be larger than or equal to the minimum photolithographic resolution used in defining the implantation area for the emitter and collector regions. As an example, in a BiCMOS integrated circuit formed by a 0.8 .mu.m process, the base width of a lateral bipolar transistor would be -4 times larger than the 0.2 .mu.m base width typically obtained in a vertical bipolar transistor.
Furthermore, a conventional lateral bipolar transistor suffers poor efficiency because when the emitter-base junction is forward biased, carriers are launched in all directions from the emitter, not only towards the emitter, but also towards the substrate. In the layout of a conventional lateral transistor the collector is made to encircle the emitter to improve the collector efficiency.
Various schemes have been investigated to improve the performance of lateral bipolar transistors, for example, as discussed in U.S. Pat. No. 5,081,517 to Contiero et al., issued 14 Jan. 1992 entitled "Mixed Technology Integrated Circuit Comprising CMOS Structure and Efficient Lateral Bipolar Transistors With a High Early Voltage and Fabrication Thereof". In a large dimensional lateral bipolar transistor, i.e. in a low density integration, the collector and emitter extend relatively deeply into the well region and the emitter current is efficiently collected by the collector. However, if a lateral bipolar transistor is integrated with a shallow junction MOSFET, and has a correspondingly shallow collector region, the collector efficiency may be very poor. In the lateral bipolar transistor of Contiero et al., a collector "extension" region of the lateral bipolar transistor is provided. The latter extends relatively deeply into the well region compared with a CMOS junction region, to intercept the emitter current and gather it to the collector, and thus improve collector efficiency. An annular diffusion region provides a collector which encircles the emitter region and thus increases the collector efficiency, and further reduces the proportion of the emitter current which is lost to the substrate.
In another approach, it is known to form trench based lateral PNP bipolar transistors in which an emitter is provided by a sidewall of a trench to increase the injecting area and provide a more efficient cross-section for a high performance PNP. For example, a method of forming higher performance lateral PNP transistor with buried base contact is described in U.S. Pat. No. 5,198,376 issued 30 Mar. 93 to Divakaruni et al. However, provision of trenches adds to the number of processing steps, and the process may not as easily be integrated into a BiCMOS process including shallow junction CMOS transistors.
Another approach to improving performance of bipolar transistors is described in U.S. Pat. No. 5,422,502 to Kovacic et al. issued 6 Jun. 1995 entitled "Lateral bipolar transistors" Nevertheless the latter approach is based on a silicon/germanium heterostructure, which requires more complex manufacturing.